Field
This disclosure relates generally to semiconductor devices, and more specifically, to stacked integrated circuit systems in a package, and methods therefor.
Related Art
Three-dimensional integrated circuit (ICs) systems in package (SiP) may comprise a number of package layers stacked one upon another with inter-package connection comprising through-vias. Three-dimensional IC SiP packaging technologies usually have lengthy process. For example, a three-dimensional fan-out wafer level package requires panels containing one or more components to be joined together, through-package vias to be formed, and build-up layers to be formed. In addition, components on different layers of the package can have different heights or thicknesses. The complex processes required to form SiPs can present manufacturing challenges, increased cost, and reliability issues. It is therefore desirable to develop three-dimensional packaging technology with reduced process complexity to improve manufacturability, and reduce cost and cycle time.